1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device that belongs to a small semiconductor package called a CSP (Chip Size Package) and a method of manufacturing the same.
2. Description of the Related Art
In recent years, semiconductor devices called CSP (Chip Size Package) have been developed as portable electronic devices represented by cellular phones decrease their sizes. In a CSP, a passivation film (intermediate insulating film) is formed on the upper surface of a bare semiconductor device having a plurality of connection pads for external connection. Opening portions are formed in the passivation film in correspondence with the connection pads. Interconnections are connected to one-terminal sides the connection pads at through the opening portions. Columnar electrodes for external connection are formed on the other-terminal sides of the interconnections. The spaces between the columnar electrodes for external connection are filled with a sealing material. According to this CSP, when solder balls are formed on the columnar electrodes for external connection, the device can be bonded to a circuit board with connection terminals by the face-down method. The mounting area can be almost the same as the size of the bare semiconductor device. The CSP can therefore greatly decrease the sizes of electronic devices as compared to the conventional face-up bonding method using wire bonding. U.S. Pat. No. 6,467,674 discloses a method in which, to increase the productivity, a passivation film, interconnections, external connection electrodes, and a sealing material are formed on a semiconductor substrate in a wafer state. After solder balls are formed on the upper surfaces of the external connection electrodes that are exposed without being covered with the sealing material. Then, the wafer is cut along dicing lines to form individual semiconductor devices.
The conventional semiconductor device raises the following problems when the number of external connection electrodes increases as the degree of integration becomes higher. As described above, in a CSP, the external connection electrodes are arrayed on the upper surface of a bare semiconductor device. Hence, the external connection electrodes are normally arrayed in a matrix. In a semiconductor device having many external connection electrodes, the size and pitch of the external connection electrodes become extremely small. Because of this disadvantage, the CSP technology cannot be applied to devices that have a large number of external connection electrodes relative to the size of the bare semiconductor device. If the external connection electrodes have extremely small size and pitch, alignment to the circuit board is difficult. There are also many fatal problems such as a low bonding strength, short circuit between electrodes in bonding, and destruction of external connection electrodes which is caused by stress generated due to the difference in coefficient of linear expansion between the circuit board and the semiconductor substrate normally formed from a silicon substrate.